IEEE 1076.6-2004

The standard describes a standard syntax and semantics for VHDL RTL synthesis. It defines the subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis and defines the semantics of that subset for the synthesis domain. The intent of this revision is to include a maximum subset of VHDL that can be used to describe synthesizable RTL logic. This includes considering new features introduced by IEEE Std 1076-1993, IEEE Std 1076-2002, new semantics based on algorithmic styles rather than template-driven, and a set of synthesis attributes that can be used to annotate an RTL description.