IEEE Bundle-2018

The 1450 test interface (STIL) and Core Test language bundle provides an interface between digital test generation tools and test equipment and interface between digital test generation tools and test equipment. It defines structures in STIL for specifying the DC conditions for a device under test. The STIL environment supports transferring tester-independent test programs to a specific ATE system. The Core Test Language (CTL) is a language created for a System-on-Chip flow (or SoC flow), where a design created by one group is reused as a sub-design of a design created by another group. It defines how the necessary information is passed from scan insertion to pattern generation and from pattern generation to diagnosis such that different tool vendors could be used for each step independent of on-chip scan compression logic used. It defines language constructs sufficient to represent the context of a memory core and of the integration of that memory core into an System-on-Chip flow (SoC).