• JEDEC JEP154

JEDEC JEP154

GUIDELINE FOR CHARACTERIZING SOLDER BUMP ELECTROMIGRATION UNDER CONSTANT CURRENT AND TEMPERATURE STRESS

JEDEC Solid State Technology Association, 01/01/2008

Publisher: JEDEC

File Format: PDF

$38.00$76.00


Published:01/01/2008

Pages:34

File Size:1 file , 370 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This document describes a method to test the electromigration (EM) susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages. The method is valid for Sn/Pb eutectic, high Pb, and Pb-free solder bumps. The document discusses the advantages and concerns associated with EM testing, as well as options for data analysis.

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