JEDEC JEP183A

SiC MOSFETs have threshold voltage hysteresis, which must be carefully considered when evaluating the VT shift caused by stress tests such as bias-temperature instabilities (BTI) [1]. This publication describes the guidelines for VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis.
The test methods can be applied to the following:
• N-channel SiC MOSFET (vertical structure)
• Wafer and package levels