JEDEC JESD22-B109B

FLIP CHIP TENSILE PULL

JEDEC Solid State Technology Association, 07/01/2014

Publisher: JEDEC

File Format: PDF

$28.00$56.00


Published:01/07/2014

Pages:16

File Size:1 file , 72 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency of the chip join process. This test method is a destructive test.

More JEDEC standard pdf

JEDEC JEB 19

JEDEC JEB 19

RECOMMENDED CHARACTERIZATION OF MOS SHIFT REGISTERS

$25.00 $51.00

JEDEC JESD398 (R2009)

JEDEC JESD398 (R2009)

MEASUREMENT OF SMALL VALUES OF TRANSISTOR CAPACITANCE

$27.00 $54.00

JEDEC EIA 397

JEDEC EIA 397

RECOMMENDED STANDARD FOR THYRISTORS

$114.00 $228.00

JEDEC JESD 372 (R2009)

JEDEC JESD 372 (R2009)

THE MEASUREMENT OF SMALL-SIGNAL VHF-UHF TRANSISTOR ADMITTANCE PARAMETERS

$27.00 $54.00