• JEDEC JESD47I

JEDEC JESD47I

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

JEDEC Solid State Technology Association, 04/01/2011

Publisher: JEDEC

File Format: PDF

$36.00$72.00


Published:01/04/2011

Pages:28

File Size:1 file , 260 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.

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