• JEDEC JEP143C

JEDEC JEP143C

SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIES

JEDEC Solid State Technology Association, 07/01/2012

Publisher: JEDEC

File Format: PDF

$38.00$76.00


Published:01/07/2012

File Size:1 file , 340 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

The purpose of this publication is to provide an overview of some of the most commonly used systems and test methods historically performed by manufacturers to assess and qualify the reliability of solid state products. The appropriate references to existing and proposed JEDEC (or EIA) standards and publications are cited. This document is also intended to provide an educational background and overview of some of the technical and economic factors associated with assessing and qualifying microcircuit reliability.

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