• JEDEC JESD22-B109A

JEDEC JESD22-B109A

FLIP CHIP TENSILE PULL

JEDEC Solid State Technology Association, 01/01/2009

Publisher: JEDEC

File Format: PDF

$28.00$56.00


Published:01/01/2009

Pages:16

File Size:1 file , 67 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency of the chip join process. This test method is a destructive test,

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