JEDEC JESD51-4A

Thermal Test Chip Guideline (Wire Bond Type Chip)

JEDEC Solid State Technology Association, 06/01/2019

Publisher: JEDEC

File Format: PDF

$33.00$67.00


Published:01/06/2019

Pages:26

File Size:1 file , 1.2 MB

Note:This product is unavailable in Russia, Ukraine, Belarus

The purpose of this document is to provide a design guideline for thermal test chips used for integrated circuit (IC) and transistor package thermal characterization and investigations. The intent of this guideline is to minimize the differences in data gathered due to nonstandard test chips and to provide a well-defined reference for thermal investigations.

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