JEDEC JESD82-8.01

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CU877 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CU877 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This document includes minor editorial changes as noted in Annex A, page 16.