JEDEC JEP69-B (R1999)

PREFERRED LEAD CONFIGURATION FOR FIELD-EFFECT TRANSISTORS

JEDEC Solid State Technology Association, 11/01/1973

Publisher: JEDEC

File Format: PDF

$24.00$48.00

Published:01/11/1973

Pages:8

File Size:1 file , 87 KB

Note:This product is unavailable in Russia, Ukraine, Belarus

This publication indicates preferred pinouts for FETs in various package designs.

BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICS FOR HANDHELD ELECTRONIC PRODUCTS

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Potential Failure Mode and Effects Analysis (FMEA)

$36.00 $72.00

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

$38.00 $76.00

Graphics Double Data Rate (GDDR6) SGRAM Standard

$114.00 $228.00